Conventional analog disconnect detection circuitry is typically implemented in the analog front end of high speed serial communication circuitry such as, for example, that defined in accordance with USB standard 2.0, to detect a high speed disconnect state on a data line. An example embodiment of conventional analog disconnect detection circuitry includes level-shifting circuitry, comparator circuitry and output circuitry. The level-shifting circuitry generally shifts the voltage level of two input signals by the value of a detection threshold, generates two sets of differential signals, and mitigates the effect of input differential signal common-mode voltage on the detection operation. The comparator circuitry generally compares each set of differential signals generated by the level-shifting circuitry and produces signals indicating when the absolute difference between the two input signals is greater than a reference voltage. Finally, the output circuitry generates a disconnect signal corresponding to an absolute disconnect condition, thereby signaling detection of the disconnection state.
The conventional analog disconnect detection circuit operates with a supply voltage that, when compared to the input detection threshold voltage, is relatively large. However, when the supply voltage is reduced, performance of the conventional analog disconnect detection circuitry is significantly degraded. Accordingly, the conventional analog disconnect detection circuitry is limited to implementations in which the supply voltage is relatively large with respect to the input detection threshold voltage. Furthermore, analog disconnect detection circuits implemented with high supply voltages typically utilize thick gate oxide transistors to mitigate reliability issues. The use of thick gate oxide transistors obstruct efforts to streamline the analog disconnect detection circuits for application in SOC platforms where thick gate oxide devices are not supported.